1. Field of the Invention
The present invention relates to intermediate potential generators, and particularly to a device for generating an intermediate potential between an operating power supply potential Vcc and a ground potential GND. More particularly, the present invention relates to a device for generating an intermediate potential for precharging a bit line, an internal data bus line, and a cell plate of a memory cell capacitor in a dynamic random access memory.
2. Description of the Background Art
FIG. 15 is a schematic diagram showing the structure of a conventional intermediate potential generator. The intermediate potential generator shown in FIG. 15 is described, for example, in IEEE, Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 465-470.
Referring to FIG. 15, the intermediate potential generator includes a reference potential generating stage 30 generating a first reference potential (1/2) Vcc+Vtna and a second reference potential (1/2) Vcc-.vertline.Vtpa.vertline., and a drive stage 40 receiving the first and second reference potentials from reference potential generating stage 30 to provide an intermediate potential (1/2) Vcc to an output node 50. Both the reference potential generating stage 30 and drive stage 40 are driven by a power supply potential Vcc and a ground potential GND respectively provided from a power supply potential node 10 and a ground potential node 20.
Reference potential generating stage 30 includes a voltage dividing stage and a bias stage. The voltage dividing stage includes a resistance element 31 formed of e.g. polysilicon, and connected between power supply potential node 10 and an internal node 32, and a resistance element 33 formed of e.g. polysilicon, and connected between node 32 and ground potential node 20. Resistance elements 31 and 33 are formed of identical material, and have an identical resistance value. A potential of node 32, therefore, is Vcc/2.
The bias stage includes a resistance element 34 connected between power supply potential node 10 and a first internal output node 35, and an n-channel MOS transistor 36 connected between nodes 35 and 32 and having its gate connected to node 35. Resistance element 34 has a high resistance value not less than 1 M.OMEGA.. Transistor 36 has a threshold voltage Vtna.
The bias stage further includes a p-channel MOS transistor 37 connected between node 32 and an internal output node 38 and having its gate connected to output node 38, and a resistance element 39 formed of e.g. polysilicon, and connected between node 38 and ground potential node 20. Transistor 37 has a negative threshold voltage Vtpa. Resistance element 39 has a high resistance value not less than 1 M.OMEGA. as resistance element 34 has.
Drive stage 40 includes a push-pull current-mirror amplifying stage and a push-pull output stage. The push-pull current-mirror amplifying stage includes a p-channel MOS transistor 40a connected between power supply potential node 10 and a node 40b and having its gate connected to a node 40b; an n-channel MOS transistor 40c connected between node 40b and an output node 50, and receiving at its gate the first reference potential generated from internal output node 35 of reference potential generating stage 30; a p-channel MOS transistor 40d connected between output node 50 and a node 40e, and receiving at its gate the second reference potential from internal output node 38 of the reference potential generating stage; and an n-channel MOS transistor 40f connected between node 40e and ground potential node 20, and having its gate connected to node 40e.
A threshold voltage vtnb of transistor 40c is made slightly larger than the threshold voltage Vtna of transistor 36 included in reference potential generating stage 30. A threshold voltage Vtpb of transistor 40d is made slightly smaller than the threshold voltage Vtpa of transistor 37 included in reference potential generating stage 30.
The push-pull current-mirror amplifying stage further includes a p-channel MOS transistor 40g connected between power supply potential node 10 and a node 40h, and having its gate connected to node 40b; an n-channel MOS transistor 40i connected between node 40h and output node 50, and having its gate connected to node 40h; a p-channel MOS transistor 40j connected between output node 50 and a node 40p, and having its gate connected to node 40p; and an n-channel MOS transistor 40r connected between node 40p and ground potential node 20, and having its gate connected to node 40e.
.beta., which is a constant proportional to gate width/gate length, of transistor 40g is set to k times that of transistor 40a. Transistors 40a and 40g constitute a current-mirror circuit having the mirror ratio k.
.beta. of transistor 40r is set to k times that of transistor 40f. Transistors 40f and 40r constitute a current-mirror circuit having the mirror ratio k.
The push-pull output stage includes an n-channel MOS transistor 40s connected between power supply potential node 10 and output node 50 and having its gate connected to node 40h, and a p-channel MOS transistor 40t connected between output node 50 and ground potential node 20 and having its gate connected to node 40p. .beta. of transistor 40s is set to m times that transistor 40i. Transistors 40i and 40s constitute a current-mirror circuit having the mirror ratio m. .beta. of transistor 40t is set to m times that of transistor 40j. Transistors 40j and 40t constitute a current-mirror circuit having the mirror ratio m. Description will now be made on the operation of the intermediate potential generator shown in FIG. 15.
In reference potential generating stage 30, resistance elements 31 and 33 have an identical resistance value, so that a potential N1 of node 32 is Vcc/2.
Each of resistance elements 34 and 39 has a high resistance value of approximately 1 M.OMEGA.. In the case of the power supply potential Vcc of 3V, a current flowing through transistors 36 and 37 is 3V/(1 M.OMEGA.+1 M.OMEGA.)=1.5 .mu.A, approximately. Each of transistors 36 and 37 has its gate and drain connected to each other, and operates in a saturation region. A current Ids flowing through the MOS transistor in the saturation region, therefore, is described by: EQU Ids=.beta.(Vgs-Vth).sup.2,
where Vgs is a gate to source voltage of MOS transistor and Vth is a threshold voltage. This current value is very small. Accordingly, the gate to source voltage, namely a voltage between nodes 32 and 35, of n-channel MOS transistor 36 approximates to the threshold voltage Vtna, so that a potential N2 of node 35 approximates to (1/2) Vcc+Vtna.
Similarly, in p-channel MOS transistor 37, a gate to source voltage thereof, namely a voltage between nodes 38 and 32 approximates to the threshold voltage Vtpa, so that a potential N3 of node 38 approximates to (1/2) Vcc-.vertline.Vtpa.vertline., approximately.
In drive stage 40, a threshold voltage Vtnb of n-channel MOS transistor 40c is set slightly larger than the threshold voltage Vtna of n-channel MOS transistor 36. A threshold voltage Vtpb of p-channel MOS transistor 40d is set slightly smaller than the threshold voltage Vtpa of p-channel MOS transistor 37.
In the case of a potential of output node 50 being approximately the intermediate potential (1/2) Vcc, transistors 40c and 40d are both brought into the OFF state.
When the potential of output node 50 is not more than (1/2) Vcc-(Vtna-Vtnb), n-channel MOS transistor 40c is brought into the ON state, while p-channel MOS transistor 40t is held in the OFF state. Accordingly, a current I1 flows from power supply potential node 10 via p-channel MOS transistor 40a and n-channel MOS transistor 40c to output node 50.
Transistor 40g constitutes a current-mirror circuit having the mirror ratio k together with transistor 40a, so that a mirror current k.multidot.I1 flows from power supply potential node 10 via transistors 40g and 40i to output node 50. Also, transistor 40s constitutes a current-mirror circuit having the mirror ratio m together with transistor 40i, so that a mirror current k.multidot.m.multidot.I1 flows from power supply potential node 10 via transistor 40s to output node 50. The potential of output node 50 rises up to (1/2) Vcc+Vtna-Vtnb because of the current charge through these three paths, thereby rendering transistor 40c and thus all the transistors constituting the current-mirror circuit OFF, which prevents a charging current from power supply potential 10 to output node 50.
When the potential of output node 50 exceeds (1/2) Vcc+.vertline.Vtpb.vertline.-.vertline.Vtpa.vertline., p-channel MOS transistor 40d is brought into the ON state, while n-channel MOS transistor 40c is held in the OFF state. A current I2 flows from output node 50 via transistors 40d and 40f to ground potential node 20. Transistor 40r constitutes a current-mirror circuit having the mirror ratio k, together with transistor 40f, so that a mirror current k.multidot.I2 flows from output node 50 via transistors 40j and 40r to ground potential node 20.
P-channel MOS transistor 40t also constitutes a current-mirror circuit having the mirror ratio m, together with p-channel MOS transistor 40j, so that a mirror current k.multidot.m.multidot.I2 flows from output node 50 via transistor 40t to ground potential node 20. Consequently, output node 50 is discharged at high speed so that the potential thereof drops.
When the potential of output node 50 drops to (1/2) Vcc+.vertline.Vtpb.vertline.-.vertline.Vtpa.vertline., p-channel MOS transistor 40t is brought into the OFF state, so that a current path between output node 50 and ground potential node 20 is cut off.
The potential VOUT of output node 50 is represented by: EQU (1/2) Vcc+Vtna-Vtnb&lt;VOUT&lt;(1/2) Vcc+.vertline.Vtpb.vertline.-.vertline.Vtpa.vertline. (1)
The values .vertline.Vtna-Vtnb.vertline. and .vertline.Vtpb.vertline.-.vertline.Vtpa.vertline. are very small. Accordingly, the potential VOUT of output node 50 is approximately (1/2) Vcc.
In reference potential generating stage 30 of the intermediate potential generator structured as the above, however, a current normally flows from power supply potential node 10 into ground potential node 20 via resistance elements 31 and 33. Also, a current normally flows from power supply potential node 10 to ground potential node 20 via resistance element 34, n-channel MOS transistor 36, p-channel MOS transistor 37, and resistance element 39. In order to reduce the regular current flow, a resistance value of each of resistance elements 31, 33, 34 and 39 should be made large. In the case of these resistance elements being formed of polysilicon, since a polysilicon interconnection layer for resistance elements is formed in the identical process steps with an ordinary polysilicon interconnection layer for signal transmission, the sheet resistance values thereof are identical. The sheet resistance of the polysilicon interconnection layer cannot be made large for prevention of propagation delay of a signal. As a result, the length of the polysilicon interconnection layer must be made considerably large for forming a resistance element having a higher resistance value, which increases a layout area for resistance elements 31, 33, 34 and 39.
The use of a channel resistance of a MOS transistor can be considered as a solution for such increase of the layout area of the resistance element. In general, a resistance element having a small layout area and a high resistance value can be implemented by the use of a channel resistance of a MOS transistor.
FIG. 16 shows the structure of an intermediate potential generator with a channel resistance of a MOS transistor as a resistance element. Generally, a p-channel MOS transistor has its backgate connected to power supply potential Vcc, while an n-channel MOS transistor has its backgate connected to ground potential GND. Usually, in the structure of a resistance element, a p-channel MOS transistor is used for a MOS transistor connected to power supply node 10, and an n-channel MOS transistor is used for a resistance element connected to ground potential node 20.
In FIG. 16, a p-channel MOS transistor 31a is connected between power supply potential node 10 and a node 32, and an n-channel MOS transistor 33a is connected between node 32 and ground potential node 20. The gate of transistor 31a is connected to ground potential node 20. The gate of transistor 33a is connected to power supply potential node 10.
Similarly, a p-channel MOS transistor 34a is connected between power supply potential node 10 and a first internal output node 35. An n-channel MOS transistor 39a is connected between a second output node 38 and ground potential node 20. The gate of transistor 34a is connected to ground potential node 20, and the gate of transistor 39a is connected to power supply potential node 10.
In the reference potential generating stage shown in FIG. 16, the channel resistances of transistors 31a and 33a should be identical, as well as the channel resistances of transistors 34a and 39a should be identical.
However, a p-channel MOS transistor and an n-channel MOS transistor are different in the manufacturing process steps. It is, therefore, very difficult to make the channel resistances of the n-channel MOS transistor and the p-channel MOS transistor equal, due to variation in parameter, that is, variation in mask offset and impurity concentration, and the like. Therefore, first node 32 cannot be set accurately to the intermediate potential (1/2) vcc, so that the first and second reference potentials cannot be provided accurately.
When n-channel MOS transistors are employed in place of p-channel MOS transistors 31a and 34a, they should have their gates connected to power supply potential node 10, and have their backgates connected to ground potential node 20. In this case, the n-channel MOS transistor connected to the power supply potential node and that connected to ground potential node have different drain potentials and backgate to source voltages, so that they have different operating characteristics. Consequently, exactly equal channel resistances cannot be implemented.
Referring back to FIG. 15, when the potential VOUT of output node 50 satisfies the expression (1), n-channel MOS transistor 40c and p-channel MOS transistor 40d in drive stage 40 are in the OFF state. Still in this case, since transistors 40c and 40d are not in the complete OFF state, a sub-threshold current Is flows from power supply potential node 10 via p-channel MOS transistor 40a and n-channel MOS transistor 40c to output node 50. The sub-threshold current Is also flows from output node 50 via p-channel MOS transistor 40d and n-channel MOS transistor 40f to ground potential node 20.
Such a sub-threshold current Is is multiplied by the factor of k by p-channel MOS transistor 40g, so that a current having a magnitude of k.multidot.Is flows through n-channel MOS transistor 40i from power supply potential node 10 to output node 50. The mirror current k. Is of the sub-threshold current Is is further multiplied by the factor of m by transistor 40s, so that a current having a magnitude of k.multidot.m.multidot.Is from power supply potential node 10 to output node 50.
Also, transistors 40f and 40r constitute a current-mirror circuit, so that a sub-threshold current of k.multidot.Is flows from output node 50 via transistors 40j and 40r to ground potential node 20. This sub-threshold current further multiplied by the factor of m by transistor 40t, so that a current of k.multidot.m.multidot.Is flows from output node 50 to ground potential node 20.
Specifically, in drive stage 40, a current having a magnitude of (1+k+k.multidot.m) Is flows from power supply potential node 10 to ground potential node 20 at a steady state where the intermediate potential (1/2) Vcc is generated, causing increase of power consumption at the steady state.
In order to reduce power consumption at a steady state, the threshold voltage Vtnb of n-channel MOS transistor 40c and the absolute value .vertline.Vtpb.vertline. of the threshold voltage of p-channel MOS transistor 40d can be large so as to reduce a sub-threshold current flowing through transistors 40c and 40d. In such a case, however, .vertline.Vtna-Vtnb.vertline. and .vertline..vertline.Vtpb.vertline.-.vertline.Vtpa.vertline..vertline. become large in the expression (1), resulting in large deviation of the potential VOUT of output node 50 from the intermediate potential (1/2) Vcc.